1. Field of the Invention
The present invention relates to a semiconductor memory and, more specifically, to techniques particularly effectively applied to pseudostatic RAMs (random access memories).
2. Description of the Related Art
A known pseudostatic RAM is designed on the basis of a dynamic RAM which can be constructed in a large scale of integration, and has an interface compatibility with an ordinary static RAM. The pseudostatic RAM has, in addition to an ordinary read/write mode, an address refresh mode and an autorefresh mode in which a refreshing action is executed once in response to an external control action, and a self-refresh mode in which a self-controlled refreshing action is executed periodically, for example, while the pseudostatic RAM is backed up by a battery. The pseudostatic RAM is provided internally with a refresh counter for sequentially specifying word lines for refreshing action in the autorefresh mode and the self-refresh mode, and a refresh timer circuit for periodically starting the refreshing action in the self-refresh mode.
The pseudostatic RAM having the autorefresh and self-refresh modes is described, for example, in "Hitachi IC Memory Data Book", Hitachi, Ltd., pp 229-234, March, 1987.
The mean current consumption of the memory arrays of the pseudostatic RAM or the like in the self-refresh mode increases approximately in proportion to the reciprocal of the refresh period, i.e., the number of refresh cycles in a unit time. The refresh period in the self-refresh mode is dependent on the intrinsic information holding ability of the memory cells and the stability of the refresh timer circuit for setting the refresh period. Such conditions are restrictions on the reduction of the power consumption of the pseudostatic RAM or the like in operation backed up by batteries.
Prior to the present invention, the inventors of the present invention intended to stabilize the refresh period of the pseudostatic RAM and to increase the refresh period as near to the intrinsic information holding ability of the memory cells as possible by constructing the refresh timer circuit of an oscillation circuit, which is less dependent on the supply voltage, and a refresh timer counter circuit which counts the pulses of a pulse signal provided by the oscillation circuit and generates a predetermined refresh start signal, and by selectively opening corresponding fuse means to set an optional initial count for the refresh timer counter circuit.
However, the operating current of the oscillation circuit is limited, and the oscillation circuit needs a capacitor having a comparatively long charging or discharging period, and a comparatively large resistance, hence a comparatively long polycrystalline silicon resistor must necessarily be formed on a semiconductor substrate. Accordingly, the discharge current varies or the bumping (varying) of the supply voltage cannot be absorbed rapidly due to a large substrate capacitance, which is parasitic to the semiconductor substrate and the polycrystalline silicon resistor causing the variation of the frequency of oscillation of the oscillation circuit, for example, when the supply voltage applied to the oscillation circuit bumps (varies) during the discharge period of the capacitor. Therefore, the frequency of oscillation of the oscillation circuit must have a margin in relation with the information holding ability of the memory cells.
Although the oscillation circuit and refresh timer counter circuit of the pseudostatic RAM is capable of selectively changing the refresh period of the pseudostatic RAM, there is no means for testing and confirming the oscillation characteristics and variation characteristics. Accordingly, the refresh period is set inevitably by a trial-and-error method unless data of those characteristics is available. This fact, similarly, requires the frequency to be set with a margin in relation with the information holding ability of the memory cells, restricts the reduction of the power consumption of the pseudostatic RAM and increases the amount of work required for testing the pseudostatic RAM.